Prof. Haris Volos
Prof. Haris Volos
Head of the COAST Research Group
volos.haris@ucy.ac.cy
haris-volos-57b4b527
0000-0002-3777-0012
hvolos
Q4Sn28AAAAAJ
Department of Computer Science
Office FST 01 115
1 Panepistimou Avenue
Aglantzia, Nicosia 2109, Cyprus
I am an Assistant Professor and a Marie Sklodowska-Curie Fellow at the University of Cyprus in the Department of Computer Science.
My research focuses on computer architecture and operating systems, with a particular emphasis on the interaction between hardware architecture and systems software, data-centric computing, and heterogeneous memory systems.
I lead the COAST research group that investigates the interaction of hardware architecture and systems software.
Previously, I worked as a software engineer at Google, Mountain View, USA (2018-2019) and as a research engineer at Hewlett Packard Labs, Palo Alto, USA (2013-2018).
I received my Ph.D. (2012) and M.Sc. (2007) in Computer Sciences from the University of Wisconsin-Madison. I obtained my engineering degree in Electrical and Computer Engineering (2005) from the National Technical University of Athens (Metsovion).
Publications
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IISWCTaming Performance Variability caused by Client-Side Hardware ConfigurationIn IISWC ’24: Proceedings of the 2024 IEEE International Symposium on Workload Characterization 2024
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PLDIPanthera: Holistic Memory Management for Big Data Processing over Hybrid MemoriesIn PLDI ’19: Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation 2019
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ASPLOSAn analysis of persistent memory use with WHISPERIn ASPLOS ’17: Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems 2017
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NVMWHands-off persistence system (HOPS)In NVMW ’17: 8th Annual Non-Volatile Memories Workshop 2017
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NVMWHow Applications Use Persistent MemoryIn NVMW ’17: 8th Annual Non-Volatile Memories Workshop 2017
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ICPEInterconnect emulator for aiding performance analysis of distributed memory applicationsIn ICPE ’16: Proceedings of the 7th ACM/SPEC on International Conference on Performance Engineering 2016
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MASCOTSInterSense: Interconnect performance emulator for future scale-out distributed memory applicationsIn MASCOTS ’15: Proceedings of the 2015 IEEE 23rd International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems 2015
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ICPEA framework for emulating non-volatile memory systems with different performance characteristicsIn ICPE ’15: Proceedings of the 6th ACM/SPEC on International Conference on Performance Engineering 2015
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MIDDLEWAREQuartz: A Lightweight performance emulator for persistent memory softwareIn Middleware ’15: Proceedings of the 16th International Middleware Conference 2015
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EuroSysAerie: Flexible file-system interfaces to storage-class memoryIn EuroSys ’14: Proceedings of the 9th ACM European conference on Computer systems 2014
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VLDBIn-memory performance for big dataPVLDB: Proceedings of the Very Large Data Bases Endowment 2014
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APSysStorage-class memory needs flexible interfacesIn APSys ’13: Proceedings of the 4th Asia-Pacific Workshop on Systems 2013
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ASPLOSApplying transactional memory to concurrency bugsIn ASPLOS ’12: Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems 2012
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ASPLOSMnemosyne: Lightweight persistent memoryIn ASPLOS ’11: Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems 2011
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NVMWStorage systems for storage-class memoryIn NVMW ’11: 2nd Annual Non-Volatile Memories Workshop 2011
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ECOOPNePaLTM: Design and implementation of nested parallelism for transactional memory systemsIn ECOOP ’09: Proceedings of the 23rd European Conference on Object-Oriented Programming 2009
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EuroSysxCalls: Safe I/O in memory transactionsIn EuroSys ’09: Proceedings of the 4th ACM European conference on Computer Systems 2009
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IEEE MicroPerformance Pathologies in Hardware Transactional MemoryIEEE Micro 2008
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TRANSACTPathological interaction of locks with transactional memoryIn TRANSACT ’08: 3rd ACM SIGPLAN Workshop on Transactional Computing 2008
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TRANSACTOS Support for virtualizing hardware transactional memoryIn TRANSACT ’08: 3rd ACM SIGPLAN Workshop on Transactional Computing 2008
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ISCAPerformance pathologies in hardware transactional memoryIn ISCA ’07: Proceedings of the 34th International Symposium on Computer Architecture 2007
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HPCALogTM-SE: Decoupling hardware transactional memory from cachesIn HPCA ’07: Proceedings of the 13th International Symposium on High Performance Computer Architecture 2007